21. The Starlog Project At The University Of Waikato Declarative temporal logic programming language for general purpose programming, simulation, modeling reactive systems. Starlog programs consist of 2 components a set of timed facts, a set of temporal logic rules. Somewhat like Prolog. http://www.cs.waikato.ac.nz/Research/starlog/index.html

A new Logic Programming Language The Starlog Project What is Starlog? Motivation Starlog Concepts Examples ... Department Home What is Starlog? Starlog is a pure-logic programming language designed to overcome some of the problems inherient in traditional approaches to logic programming. As a result, Starlog is designed to be a general purpose programming language, and is particularly useful for simulation, and for modelling reactive systems. Although most logic programming languages (e.g. Prolog) are query driven (i.e. are evaluated "top-down"), Starlog programs are evaluated "bottom-up". That is, as a Starlog program executes, it builds a model of all the true facts that can be derived from rules in the program. The evaluation of Starlog programs is controlled using a stratification order. Motivation Traditionally, logic programming languages have never been able to compete with the popularity of other language paradigms. We attribute this to: Most implementations of logic programs being less efficient at run time than equivalent programs from other language paradigms. The introduction of extra-logical operators that improve efficiency often break the declarative semantics of logic programs.

22. Diagnosing Java Code: Assertions And Temporal Logic In Java Programming One way to fill this gap is with temporal logic, a formalism used to describe how a program state will change over time. In this http://www-106.ibm.com/developerworks/java/library/j-diag0723.html

var title = "Diagnosing Java code: Assertions and temporal logic in Java programming"; var contentAreaList = "java"; var emailAbstract = "Although traditional assertions can increase the amount of checking that can be done over Java code, there are many checks you just can't perform with them. One way to fill this gap is with temporal logic, a formalism used to describe how a program state will change over time. In this article, Eric Allen discusses assertions, introduces temporal logic, and describes a tool for processing temporal logic assertions in your programs. "; var demoURL = ""; Search for: within All of dW eServer Lotus Rational Tivoli WebSphere Autonomic computing Grid computing Java technology Linux Open source Web arch. Web services Wireless XML dW forums dW Subscription alphaWorks All of IBM Search help IBM home My account developerWorks ... Java technology Diagnosing Java code: Assertions and temporal logic in Java programming Contents: Assertions and properties Temporal logic connection How to check temporal logic A timely last word ... Rate this article Related content: Magic with Merlin: Working with assertions The Fictitious Implementation bug pattern Java Modeling: A UML workbook Diagnosing Java Code columns Subscriptions: dW newsletters dW Subscription (CDs and downloads) Introduce temporal logic to assertions to supplement testing Level: Introductory Eric E. Allen

23. Homepage Of Joeri Engelfriet Vrije Universiteit Amsterdam Formal models for static and dynamic aspects of complex reasoning processes, temporal logic, and belief revision. http://www.cs.vu.nl/~joeri/

FRAMES you can access my pages from my old homepage

24. Specifications In Temporal Logic Specifications in temporal logic. temporal logic studies the structure or topology of time 13. It uses In more recent years, temporal logic has been successfully applied in various http://rutcor.rutgers.edu/~pinzon/papers/rrr1/node13.html

Next: Control Synthesis Up: Timed Transition Models Previous: The Plant Model Specifications in Temporal Logic Temporal logic studies the structure or topology of time [ ]. It uses special operators such as (``henceforth'') and (``eventually'') to describe the temporal connectives that occur in language. In more recent years, temporal logic has been successfully applied in various areas of computer science, especially software verification. (See for example [ ].) Ostroff uses Real Time Temporal Logic (RTTL) in describing the specifications for purposes of controller synthesis. RTTL is an extension of the Manna-Pnueli temporal logic [ ]. It uses the standard temporal operators and adds the proof rules needed for real-time properties. The following summary follows closely that presented in [ ]. The reader is referred to [ ] for more details on RTTL. A state-formula is any first order predicate which does not contain any temporal operators. If a state-formula evaluates to true in state s , we write . Unlike a state-formula which can be evaluated in a single state, a

25. Diagnosing Java Code: Using Temporal Logic With Bug Patterns temporal logic is a formalism used to describe how a program state will change over time. Diagnosing Java code Using temporal logic with bug patterns, http://www-106.ibm.com/developerworks/java/library/j-diag0827.html

var title = "Diagnosing Java code: Using temporal logic with bug patterns"; var contentAreaList = "java"; var emailAbstract = "Temporal logic is a formalism used to describe how a program state will change over time. In this article, his second on temporal logic and assertions, Eric Allen discusses how several of the most common bug patterns can be prevented by the use of temporal logic assertions."; var demoURL = ""; Search for: within All of dW eServer Lotus Rational Tivoli WebSphere Autonomic computing Grid computing Java technology Linux Open source Web arch. Web services Wireless XML dW forums dW Subscription alphaWorks All of IBM Search help IBM home My account developerWorks ... Java technology Diagnosing Java code: Using temporal logic with bug patterns Contents: Dangling Composite Saboteur Data Split Cleaner Orphaned Thread ... Rate this article Related content: Magic with Merlin: Working with assertions Diagnosing Java code columns Subscriptions: dW newsletters dW Subscription (CDs and downloads) Preventing common bugs with temporal logic assertions Level: Introductory Eric E. Allen

26. Julian Bradfield's Home Page University of Edinburgh Verification using temporal logics, computer-aided verification of potentially infinite systems, logics for true concurrency. http://www.dcs.ed.ac.uk/~jcb/

Julian Bradfield GnuPG public key (for routine matters)) very old PGP (2.6.2i) public key (only if you can't use GnuPG) Phone: +44 131 650 5998 Fax: +44 131 667 7209 Computer Science King's Buildings Mayfield Road Edinburgh EH9 3JZ United Kingdom I am Reader in Computer Science here at the University of Edinburgh. My first degree was in Mathematics, from Cambridge, and after doing the conversion Diploma in Computer Science, I came to Edinburgh for my Ph.D. After completing this, I was a postdoc for a couple of years, and since 1992 I've been on the teaching staff. From 1997 to 2002, I was an EPSRC Advanced Research Fellow. Research If you're interested in my research, please go to my research page Teaching In 2003-4, I am lecturing: The CS3 Operating Systems module The M.Sc. Programming in Java module Administration I am the third year course organizer. ( NOTE: All mail concerning third year course organization should be sent to cs3co (at) inf.ed.ac.uk not to my personal address.) I convene the Computing Committee I am the School representative on the College Computing Committee I am a teaching staff representative on the Senatus Academicus CSL'02 If you're looking for archived information on CSL'02, the

27. Martin Fränzle, Researcher In CS, Oldenburg University, Germany Universit¤t Oldenburg Formal methods, real-time and hybrid systems, hardware synthesis and verification, and temporal logic. http://ca.informatik.uni-oldenburg.de/~fraenzle/

Dr. Position: Till July 2002, I have been senior research assistant at the Computer Science Department of the , Germany. In August 2002, I have moved to the Technical University of Denmark as an associate professor. Please consult my new homepage for more recent information. Research interests: Real-time and hybrid control systems: high-level modelling, formal methods for analysis, specification and design, automatic verification. Temporal logic: semantics of metric-time variants, Semantic models of embedded systems and VLSI New address: Informatics and Mathematical Modelling The Technical University of Denmark Richard Petersens Plads, Bldg. 322 DK-2800 Kgs. Lyngby Denmark Tel: Fax: Last modified: Aug. 20, 2002

28. Foundations Of Temporal Logic - The WWW-site For Prior-studies frameles.htm. http://www.hum.auc.dk/prior/index2.htm

29. ANGELO MONTANARI WEB PAGE University of Udine Logical specifications of real-time systems, temporal and object-oriented databases, deductive databases, temporal representation and reasoning, modal and temporal logic, set theory. http://www.dimi.uniud.it/~montana/index.html

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30. Shmuel Katz's Home Page The Technion Language constructs for distributed programming (superimposition, multiparty interactions, reconciliations), tools for design and programming of distributed systems (debugging, domain archetypes), interleaving set temporal logic (including for cache consistency), self-stabilization and fault-tolerance, formal specification methods. http://www.cs.technion.ac.il/~katz/

CS home page Shmuel Katz's Home Page a photograph Department of Computer Science The Technion Haifa 32000, Israel +972-4-829-4322 (voice) +972-4-822-1128 or -829-4353 (fax) katz@cs.technion.ac.il Research Interests: Formal specification methods and connections among them, including issues of translations among specification notations and their effects on properties of models, Verification using convenient executions, including semi-automatic proofs built over a PVS proof environment, Language constructs for distributed programming (superimposition, multiparty interactions, reconciliations), Tools for design and programming of distributed systems(debugging, domain archetypes) Interleaving set temporal logicISTL (including for cache consistency), Self-stabilization and fault-tolerance. A list of publications For copies of most of the papers, please send me an email request. However, a postscript copy of the paper "A Mechanized proof Environment for the Convenient Computations proof Method" by Marcelo Glusman and myself, to appear in the journal Formal Methods in System Design, is available here . The article "Superimpositions and Aspect-Oriented Programming" by Marcelo Sihman and myself, to appear in the BCS Computer Journal, is available

31. Simin Nadjm-Tehrani Link¶ping University Formal methods in verification of real-time and embedded systems, including discrete and hybrid models, applications of temporal logic, symbolic model checking, automata-based decompositional proof techniques. http://www.ida.liu.se/~snt/

Linköpings universitet Department of Computer and Information Science Real-Time Systems Lab Email: simin@ida.liu.se Phone: Fax: Office: Building B, First floor, Room 3B:442-444 Real-time Systems Laboratory (RTSLAB) Department of Computer and Information Science Simin Nadjm-Tehrani is the Director of Real-time Systems Laboratory (RTSLAB) since January 2000. formal analysis of safety and fault-tolerance in safety-critical systems system availability: support for fault-tolerance in middleware survivability in critical infrastructures using self-healing agents formal verification of hybrid (discrete-continuous) models Her main interests within the field of education are: curriculum design problem-based learning (PBL) authentic examination forms women in computer science Details of current activities and publications can be found on the RTSLAB web pages Last modified on Friday January 24, 2003 by Simin Nadjm-Tehrani

32. Kono's Temporal Logic Related Information The summary for this English page contains characters that cannot be correctly displayed in this language/character set. http://rananim.ie.u-ryukyu.ac.jp/~kono/temporal-logic.html

»þ¶è´Ö»þÁêÏÀÍý(Interval Temporal Logic)¤ò»È¤¤¿¤µ¤Þ¤¶¤Þ¤Ê¥×¥í¥¸¥§¥¯¥È ¤Ë´Ø¤¹¤ë¥Ú¡¼¥¸¤Ç¤¹¡£ English Page is here Tokio-9.94 Interval Temporal Logic ¤ò»È¤¤¿¥×¥í¥°¥é¥ß¥ó¥°¥Ä¡¼¥ë Tokio Programming Language RTL-Tokio Piplelined CPU verification tool LITE Intervale Temporal Logic Verifier TEMPORAL LOGIC PROGRAMMING LANGUAGE Tokio Shinji Kono, Tatsuya Aoyagi, Masahiro Fujita, Hidehiko Tanaka, Tatsuhiko Moto-oka September 1984 Logic Programming Conference Tokio: Logic Programming Language Based on Temporal Logic and Its compilation to Prolog Masahiro Fujita, Shinji Kono, Hidehiko Tanaka, Tatsuhiko Moto-oka September 1986 Internatinal Conference on Logic Programming Automatic Verification of Interval Temporal Logic Shinji Kono TM-92-007, SONYCSL March 1992 8th British Colloquium For Theoretical Computer Science October 1992 Âè9²ó¡Öµ­¹æÏÀÍý³Ø¤È¾ðÊó²Ê³Ø¡×¸¦µæ½¸²ñ Synthesis of Contrllers from Interval Temporal Loigc Specification Masahiro Fujita Shinji Kono TR-93-11, SONYCSL October May, 1993 International Workshop on Logic Synthesis A Combination of Clasual and Non Clausal Temporal Logic Program Shinji Kono TR-93-12, SONYCSL October Aug, 1993 IJCAI-93 Workshop on Executable Modal and Temporal Logics

33. Theoretical Computer Science - Faculty Institute of Mathematical Sciences, Chennai Theory of distributed systems, temporal logics, Partial order models of concurrency, Logics of knowledge. http://www.imsc.ernet.in/~jam/

R. Ramanujam Research interests : Mathematical and philosophical logic in computer science Theory of distributed systems Temporal logics and verification Partial order models of concurrency Security protocols Logics of knowledge Some papers: Paul Krasucki and R.Ramanujam, Knowledge and the ordering of events in distributed systems, Proc. Theoretical Aspects of Reasoning about Knowledge, Morgan Kaufmann, 1994, 267-283. Click here for gzipped-.ps file Kamal Lodaya, Rohit Parikh, R.Ramanujam and P.S.Thiagarajan, A logical study of distributed transition systems, Information and Computation, Vol 119, No. 1, 1995, 91-118. Click here for gzipped-.ps file R. Ramanujam, Local knowledge assertions in a changing world, Proc. Theoretical Aspects of Rationality and Knowledge, Morgan Kaufmann, 1996, pp 1-17. Click here for gzipped-.ps file R. Ramanujam, Locally linear time temporal logic, Proc. IEEE Logic in Computer Science, New Jersey, 1996, pp 118-127. Click here for gzipped-.ps file R. Ramanujam, Trace consistency and inevitability, Proc. FST and TCS, Hyderabad, 1996, Springer LNCS 1180, pp 250-261. Click here for gzipped-.ps file

34. Research Papers University of Edinburgh Models and calculi for concurrent computation, modal and temporal logics with fixed points, verification and description of program properties. http://www.dcs.ed.ac.uk/~cps/

Colin Stirling Research Interests Models and calculi for concurrent computation, modal and temporal logics with fixed points and their applications to verification and description of program properties. Tools for Concurrency, the Edinburgh Concurrency Workbench Slides Slides on "modal and temporal logics", International Winter School on Semantics and Applications, Montevideo, Uruguay, 2003. lecture one lecture two lecture three lecture four Books Edited Plotkin, Stirling, Tofte Proof, Language, and Interaction Essays in Honour of Robin Milner MIT Press, 2000 Modal and Temporal Properties of Processes Springer (Texts in Computer Science), 2001 Recent Papers Deciding DPDA equivalence is primitive recursive ICALP 2002 Lecture Notes in Computer Science Longer draft paper With M. Lange Model checking fixed point logic with chop FOSSACS 2002 Lecture Notes in Computer Science Bisimulation and language equivalence To appear in "Logic for Concurrency and Synchronisation" Volume in Kluwer series "Trends in Logic" With M. Lange Model checking games for branching time logics Journal of Logic and Computation An introduction to decidability of DPDA equivalence FSTTCS 2001 (invited talk) Lecture Notes in Computer Science Decidability of DPDA equivalence Theoretical Computer Science With C. Morvan

35. Ryan Flannery University of Cincinnati satisfiability, first-order and temporal logic, computer science. http://ryanflannery.org

ryanflannery.org home curriculum vitae blog works ... links In Soviet Russia, Road Forks You! still waiting to get a better picture... but i've been told this one is a bit better. I'm currently a senior (5th year) student at the University of Cincinnati in the College of Engineering majoring in both Computer Science and Mathematics . My areas of interest include logic programming, artificial intelligence theory, and parallel algorithm design/analysis (...and a little game programming on the side for fun). Currently, as part of my senior design project for school, I am working on a project to create an artificially intelligent Go player. In addition to computers/mathematics, I have a penchant for philosophy, poetry, and have recently begun brewing my own beer (thanks to my brother). Resume: ( dvi pdf postscript text ... squid@fuse.net Last Edited on Sat 15 May 2004, 12:02 am

36. TIME-ROVER Provides automatic verification of protocols and reactive systems through temporal logic specifications. http://www.time-rover.com/

Home Support Papers Products Customers Contact Site Map Safety Critical Systems Ask for requirements monitoring + simulation demo! Knowledge and Intelligent Systems Ask for the knowledge and belief demo! About Time-Rover Run-time Monitoring and Verification Requirement Simulation and Simulation Interchange TLChart, Temporal-Logic, Statechart Technology Knowledege Monitoring, Reasoning and Simulation Reactive Systems Run-time Verification and Monitoring

37. Temporal Logic From FOLDOC temporal logic. logic An extension There are two types of temporal logic used branching time and linear time. The basic propositional http://www.swif.uniba.it/lei/foldop/foldoc.cgi?temporal logic

38. SRI International - Computer Science Laboratory - Ground Temporal Logic: A Logic Publications Ground temporal logic A Logic for Hardware Verification by David Cyrluk and Paliath Narendran. Lecture Notes in Computer Science, Volume 818. http://www.csl.sri.com/papers/cav94/

Computing Sciences Computer Science Laboratory Contact People ... Jobs Publications Ground Temporal Logic: A Logic for Hardware Verification by David Cyrluk and Paliath Narendran Lecture Notes in Computer Science, Volume 818. From Computer-Aided Verification (CAV '94) Edited by David Dill. Springer-Verlag, Stanford, CA. June, 1994. Abstract: We present a new temporal logic, GTL, appropriate for specifying properties of hardware at the register transfer level. We argue that this logic represents an improvement over model checking for some natural hardware verification problems. We show that the validity problem for this logic is Pi 1-1 complete. We then identify a fragment of the logic that is decidable. We show that in this fragment we are still able to encode many interesting problems, including the correctness of pipelined microprocessors. BibT E X entry: http://www.csl.sri.com/papers/cav94/ Download: cav94.ps.gz Compressed PostScript Home About Us Working with SRI Careers ... News

39. Dept. Of AI: Alumni University of Ulm Object-oriented approaches to formal specification and verification, formal specification and verification of reactive systems, component-based formal development of concurrent systems, and the temporal logic of Actions. http://www.informatik.uni-ulm.de/ki/canver.html

University of Ulm Faculty of Computer Science Dept. of Artificial Intelligence back: Staff Former Members Alumni Ercüment Canver Ercuement .Canver @icn. siemens.de joined Siemens AG, Ulm Daniela Damm damm@ifi.unizh.ch Matthias Dannenberg dannenberg@soon-systems.de co-founded soon systems GbR Dr. Axel Dold dold@tescom.de or axel.dold@gmx.de joined TESCOM GmbH, Ulm Andrea Hemprich hemprich@io-software.com joined IO Software, Freiburg Dr. Joachim Herbst joachim.j.herbst@daimlerchrysler.com DaimlerChrysler, Ulm Martin Hiller Martin.Hiller@t-systems.de joined T-Systems/Debis, Ulm Hartmut Jungholt Hartmut.Jungholt@informatik.uni-ulm.de joined SGI group, Univ. Ulm Dr. Marko Luther luther@informatik.uni-ulm.de TBA Alke Martens alke.martens@informatik.uni-rostock.de joined Univ. of Rostock Prof. Dr. Bernhard Nebel nebel@informatik.uni-freiburg.de joined Univ. of Freiburg Stephan Pfab spf@pc-plus.de Dr. Harald ruess@csl.sri.com joined SRI International, Menlo Park, CA Dr. Jussi Rintanen rintanen@informatik.uni-freiburg.de joined Univ. of Freiburg Detlef Schwier detlef@blaxxun.de

40. Temporal Logic - Wikipedia, The Free Encyclopedia temporal logic. Any logic which views time as a sequence of states, is a temporal logic, and any logic which uses only two truth values, is a binary logic. http://en.wikipedia.org/wiki/Temporal_logic

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